1. Field of the Invention
The present invention relates to a semiconductor device such as a nonvolatile memory represented by a flash EEPROM whose memory cell comprises a memory transistor and select gate transistor, or a nonvolatile memory embedded logic integrated circuit formed by integrating the nonvolatile memory and a logic circuit into one chip, and a method of fabricating the same.
2. Description of the Related Art
Jpn. Pat. Appln. KOKAI Publication No. 2002-176114 (patent reference 1) and Jpn. Pat. Appln. KOKAI Publication No. 2001-015617 (patent reference 2) describes a flash EEPROM whose memory cell comprises a memory transistor and select gate transistor. FIGS. 47(a) and 47(b) of patent reference 1 disclose an arrangement in which the gate electrode of each of a memory transistor (memory cell array region) and select gate transistor (select gate region) is formed by two polysilicon layers.
That is, each of the memory transistor and select gate transistor has a stacked gate structure formed by sequentially stacking a gate insulating film, first polysilicon layer, inter-poly insulating film, and second polysilicon layer on a semiconductor substrate. The first and second polysilicon layers of the memory transistor respectively function as a floating gate electrode and control gate electrode. A through hole is formed in the second polysilicon layer and inter-poly insulating film of the select gate transistor. An aluminum (Al) interconnection or the like formed on the second polysilicon layer connects to the first polysilicon layer through the through hole. To operate the memory transistor (to read, write, or erase data), a selection signal is applied to the gate electrode (first polysilicon layer) of the select gate transistor via the Al interconnection to turn on the select gate transistor, thereby selecting the memory transistor to be operated.
In the above arrangement, however, a space must be secured between the Al interconnection connected to the gate electrode of the select gate transistor and an Al interconnection which functions as a source line or bit line. Since this limits shrinking of memory cells, the area occupied by patterns increases, and this increases the cost.
Also, FIG. 3 of patent reference 1 and FIG. 2 of patent reference 2 disclose an arrangement in which the gate electrode of each of a memory transistor and select gate transistor is formed by two polysilicon layers, and a hole is formed in a inter-poly insulating film of the select gate transistor to form a contact between first and second polysilicon layers, thereby electrically connecting the first and second polysilicon layers. The gate electrodes of the memory transistor and select gate transistor are formed in the same fabrication steps. When forming the contact, therefore, after the second polysilicon layer is formed, the pattern of a contact hole is transferred by lithography onto that portion of a photoresist coated on the second polysilicon layer, which corresponds to the gate electrode of the select gate transistor, and the surface of the first polysilicon layer is exposed by sequentially etching the second polysilicon layer and inter-poly insulating film by RIE. After that, CVD is used to deposit polysilicon on the second polysilicon layer and on the first polysilicon layer exposed in the contact hole, thereby forming a contact portion which electrically connects the first and second polysilicon layers.
The arrangement and fabrication method as described above obviate the need for an Al interconnection or contact for backing the polysilicon layers, and can increase the degree of freedom of the layout of, e.g., source lines and bit lines, thereby shrinking memory cells.
Unfortunately, if another (third) polysilicon layer is deposited to form the contact portion for the first and second polysilicon layers as described above, the contact resistance between the polysilicon layers rises (to, e.g., about 400 Ω), and this increases the parasitic resistance of the gate electrode of the select gate transistor. In addition, the above fabrication method requires the lithography step of forming the hole in the inter-poly insulating film, and the step of additionally stacking the third polysilicon layer. This increases the fabrication cost by the cause different from the prior art described earlier.